The fabrication of advanced sub-tenth-micron devices will require replacement of the highly doped polysilicon gate electrode by new gate materials. The gate electrode stack for advanced devices should provide low sheet resistance to minimize interconnect delays, have a tunable work function to enable both n and p-type transistors to operate in surface channel mode, and prevent gate electrode depletion effects (to assure that the effective oxide thickness is equal to the physical oxide thickness).
For this, as well as other reasons, metal gate electrode stacks have been proposed for these sub-tenth-micron devices. Unfortunately, however, the conventional single-step patterning of the metal gate electrode stacks for these short gate length (e.g., sub-tenth-micron) transistors, which are often formed on ultra-thin (e.g., sub 5 nm) gate oxides, imposes a severe challenge to the etch process. Very high selectivity to SiO2 has to be achieved to avoid oxide punchthrough and subsequent damage to the silicon in the source and drain regions. Even when successfully stopped in the gate oxide, the conventional gate etch process introduces corner damage to the gate structure that needs to be annealed to guarantee good gate oxide integrity (GOI) properties of the transistor. However, it is difficult to anneal the corner damage on metal gate structures, since many metals readily oxidize in conventional oxidation processes.
Accordingly, what is needed in the art is a method for patterning metal gate structures of transistor devices that do not experience the drawbacks, particularly gate oxide punchthrough, as experienced by the prior art methods.